High Throughput Implementations of the RC6 Block Cipher Using Virtex-E and Virtex-II Devices

This short paper is devoted to the study of effective hardware architectures for the RC6 block cipher using Virtex-E and Virtex-II FPGA devices. The key point of the implementation is the design of an arithmetic operator computing f(X)=(X(2X+1))2^w. Significant speed and area improvements are obtained by taking full advantage of the small multiplier blocks available in Virtex-II devices

Multiplication-addition modulaire: algorithmes itératifs et implantations sur FPGA

This paper describes several improvements of an iterative algorithm for modular multiplication originally proposed by Jeong and Burleson. A first modification of the recurrence relation allows us to implement a fused multiply and add unit. Then, we show how to reduce the circuit area by a factor two when the operator offers the possibility to choose the modulo among a set m_1, m_2,, m_q. A new iterative algorithm making the implementation of modular exponentiation easier is eventually discussed. For 16-bit numbers, our operators perform for instance 6 millions of operations per second on a Virtex-E device while only requiring 17 slices

Modular Multiplication for FPGA Implementation of the IDEA Block Cipher

The IDEA block cipher is a symmetric-key algorithm which encrypts 64-bit plaintext blocks to 64-bit ciphertext blocks, using a 128-bit secret key. The security of IDEA relies on combining operations from three algebraic groups: integer addition modulo 2^n, bitwise exclusive or of two n-bit words, and integer multiplication modulo (2^n+1) which is the critical arithmetic operation of the block cipher. In this paper, we investigate three algorithms based on a small multiplication with a subsequent modulo correction. They are particularly well suited for the latest FPGA devices embedding small multiplier blocks, like the Virtex-II family. We also consider a multiplier based on modulo (2^n+1) adders. Several architectures of the IDEA block cipher are then described and compared from different point of view: throughput to area ratio or adequation with feedback and non-feedback chaining modes. Our fastest circuit achieves a throughput of 8.5 Gb/s, which is, to our knowledge, the best rate reported in the literature

Évaluation polynomiale en-ligne de fonctions élémentaires sur FPGA

Cet article présente une architecture matérielle pour l'évaluation de fonctions élémentaires en arithmétique en-ligne sur circuits FPGA. Les points particuliers traités sont la détermination automatique de " bons " polynômes d'approximation, et la génération automatique de la description VHDL synthétisables des opérateurs correspondants. Cette approche a été implantée et validée sur des circuits FPGA Xilinx

Horner's Rule-Based Multiplication over Fp and Fp^n: A Survey

International audienceThis paper aims at surveying multipliers based on Horner's rule for finite field arithmetic. We present a generic architecture based on five processing elements and introduce a classification of several algorithms based on our model. We provide the readers with a detailed description of each scheme which should allow them to write a VHDL description or a VHDL code generator

A Digital Identity in the Hands of Swiss Citizens

The Swiss law on electronic identity (LSIE) was rejected on March 7, 2021. Its opponents accused it of involving private companies which could thus collect citizens\u27 data and store them centrally. Six motions with identical wording were tabled on March 10, 2021: they all ask the Swiss Federal Council to set up a state-run system allowing citizens to prove their identity online in complete confidence. They stipulate that only necessary information is collected and stored in a decentralized manner. The Swiss Federal Council has recommended to Parliament to approve these motions on May 26, 2021, and wishes to propose a new e-ID solution responding to citizens\u27 concerns as soon as possible. The Federal Department of Justice and Police has been asked to draw up a first draft presenting several technical solutions and specifying their respective costs. Following the publication of a working document on September 2, 2021, a public consultation was opened. It ended on October 14, 2021, with a public debate organized at the Government House in Bern and broadcasted live on a virtual platform. Self-Sovereign Identity (SSI) is one of the solutions identified during this process. It gives the citizens control of their electronic identity: they hold credentials issued by public administrations and choose the data they wish to disclose when they authenticate with a service (they can for example prove that they are over 18 without specifying their exact date of birth). We propose here a decentralized and user-centric e-ID system based on SSI principles. Our solution embraces an open-source philosophy, fostering transparency and community involvement. We employ blockchain technology as a design pattern to establish trust and ensure the immutability of identity-related data. By design, our solution ensures the right to be forgotten by exclusively storing the digests of verifiable credentials on the blockchain. To demonstrate the feasibility and effectiveness of our SSI solution, we have developed a proof of concept leveraging the Partisia blockchain

FPGA Implementation of a Recently Published Signature Scheme

An algorithm producing cryptographic digital signatures less than 100 bits long with a security level matching nowadays standards has been recently proposed by Courtois, Finiasz, and Sendrier. This scheme is based on error correcting codes and consists in generating a large number of instances of a decoding problem until one of them is solved (about 9!=362880 attempts are needed). A careful software implementation requires more than one minute on a 2GHz Pentium 4 for signing. We propose a first hardware architecture which allows to sign a document in 0.86 second on an XCV300E-7 FPGA, hence making the algorithm practical

A Compact FPGA Implementation of the SHA-3 Candidate ECHO

We propose a compact architecture of the SHA-3 candidate ECHO for the Virtex-5 FPGA family. Our architecture is built around a 8-bit datapath. We show that a careful organization of the chaining variable and the message block in the register file allows one to design a compact control unit based on a 4-bit counter, an 8-bit counter, and a simple Finite State Machine. A fully autonomous implementation of ECHO on a Xilinx Virtex-5 FPGA requires $127$ slices and a single memory block to store the internal state, and achieves a throughput of $72$Mbps